Posts tagged as:

VHDL

Free SystemVerilog Simulators?

by Ray Salemi on September 9, 2009

The book FPGA Simulation uses code coverage as its basic measure and SystemVerilog to implement transaction-level simulation.  This raises the question of whether there are any free SystemVerilog simulators that handle code coverage. The short answer is No.  SystemVerilog is an enormous language, and while the original Verilog simulator was written by a single guy, [...]

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Adding SystemVerilog Monitors to a VHDL Test Bench

by Ray Salemi on July 27, 2009

This posting introduces the idea of putting SystemVerilog modules into a VHDL design.

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A SystemVerilog Primer for VHDL Coders

by Ray Salemi on June 24, 2009

SystemVerilog is becoming the defacto standard for test bench creation, even in cases where the DUT is VHDL.  As more and more IP becomes available in SystemVerilog, even hard core VHDL engineers will need to have at least a passing aquaintance with the language. With that in mind, I’ve created a primer that teaches the [...]

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