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Free SystemVerilog Simulators?

by Ray Salemi on September 9, 2009

The book FPGA Simulation uses code coverage as its basic measure and SystemVerilog to implement transaction-level simulation.  This raises the question of whether there are any free SystemVerilog simulators that handle code coverage. The short answer is No.  SystemVerilog is an enormous language, and while the original Verilog simulator was written by a single guy, […]

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