About Us

As an Application Engineer Consultant for Mentor Graphics, I’ve been watching engineers struggle with today’s large, complicated FPGAs.  They constantly get stuck in the lab trying to debug a design, without any of the visibility they would have if they were simulating.

I wrote FPGA Simulation: A Complete Step-by-Step Guide to help engineers overcome this problem, and I set up this website to augment the information in the book with tips and tricks that make life better.

All the articles in www.fpgasimulation.com meet three criteria:

  1. The articles on this site are short, they are 1,000 words or less.  Because if you can’t say it in 1,000 words, then you don’t know exactly what you are trying to say.
  2. The articles are focused on FPGA simulation, and the seven steps in FPGA Simulation.  They are especially be helpful for folks implementing EZTLM.
  3. All the articles and blog entries are technical and immediately useful.

I hope that the articles on the site, combined with the forums and the weekly emal newsletter will give engineers what they need to succeed with FPGA Simulation.

Submission Guideline

FPGA simulation is a complex topic, and it has room for many voices.  I hope that you will consider submitting articles to www.fpgasimulation.com.  If you become a submitting author, you will have your ariticle posted with your byline and the article will be mentioned in the weekly email newsletter.

Your article must meet the three criteria to be considered:

  1. It must be 1000 words or fewer.
  2. It must be focused on FPGA Simulation
  3. It must deliver technical content that is immediately useful.

If you’d like to submit an article, or an idea for an article, please email it to submissions@fpgasimulation.com.

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{ 6 comments… read them below or add one }

Malcolm Cheek August 5, 2009 at 3:58 am

Hi Ray, I am trying to get hold of your book in the UK, but our normal company supplier is saying it’s out of print (I suspect that’s an excuse!). Where’s the best place to get it? Thanks, Malcolm

Reply

Ray Salemi August 5, 2009 at 6:31 am
vesselin kavalov September 8, 2009 at 9:04 pm

Hi Ray,
great book! I am trying to re-educate myself into a DV guy, since nobody needs emulation gurus anymore and your book goes in like a cold beer in a hot Californian summer afternoon 😉
First time SV makes (a lot of) sense – I tried a couple of times other texts, and they were as palatable to me as rocks!
Great job!
BTW, how do I get a user name and a password in order to download the examples?

Thanx!
vess

Reply

Ray Salemi September 8, 2009 at 10:00 pm

Hi Vess,

Sorry about that. I’ve fixed the problem, you don’t need a username/password to download anymore.

Thanks for letting me know!

Ray

Reply

Nangavalli March 27, 2013 at 7:37 pm

Hi Ray,
Good book. One question about the FPGA simulation: The TinyALU in the book is the top level to simulate. The output "result" is a port out of this. If the ALU is inside the FPGA and the "result" is not at the top, how do I bring it up in the responder, for printing out?
Thanks.
Ram.

Reply

ray March 27, 2013 at 10:45 pm

Hi Ram,

There are two ways to do this with SystemVerilog:

1. You can hierarchically reference the result (top.dut.tinyalu.result)

2. You can use a bind command to "instantiate" a monitoring module in the hierarchy.

If you had a module such as

monitor_result monitor_result_i (result);

And if your tinyalu were in top.dut.

you could do

bind top.dut monitor_result monitor_result_i(result)

Both of these solutions do not require you to touch the DUT code.

VHDL 2008 added hierarchical references to VHDL.

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