FPGA Simulation Errata

To paraphrase Neil Stephenson in Cryptonomicon, getting the last typo out of a large technical book is like trying to get the last bit of water out of a discarded tire. Many people reviewed FPGA Simulation and yet, alert readers have found the following:

Page 96 refers to the wrong line of code

Line 27—The overflow signal becomes true…

Should read

Line 29—The overflow signal becomes true…

The Prime Number randomization example on page 296 will not return 2

Busted! This is true. I forgot about 2.

Table 3-2 is incorrect

Table 3-2 shows two identical transactions in the Cache2CPU: result(data,hitormiss).

There should only be one “result” transaction as is the case in the MEM2Cache channel.

There’s a little history to this error. I originally had designed this test plan with two different kinds of transactions:


Then I decided on one “result” transaction with two arguments. I did this because I looked ahead to using these transactions in a test bench and I realized that it would be easier to check an argument to a transaction than the type of the transaction.

I left two transactions in that column when I made the change.

Typo on Page 24

The last two words on page 24 should be “Test Planning” not “Code Coverage” It should read:

The fastest way to write the tests you need is to create a test plan, and that’s the subject of Step Two: Test Planning

Bug on page 95: Figure 8-3

Line 30 attempts to invert the reset signal to create an enable signal.  But all it does is prove that the enable could have been set to a constant of 1.  Line 30 should read:

enable <= '1' when (rst = '0') else '0';

Page 99 Refers to the wrong line of code

Line 37—This generic line passes our control record…

should read

Line 38—This generic line passes our control record…

Page 158 Redundant File Close

Line 12 of Figure 13-4 says:

$fclose(filea); $fclose(fileb); $fclose(fileab);

Actually since we closed filea and fileb, we don’t need to close the MCD that points to both files.

Page 350

There is a missing “=”   in the syntax for defining coverage on transitions in a covergroup.

bins bin_name = ( <value1> => <value2> );

The first “=” is missing.

(Thanks to Tony Lanier at Harris Corp for the following two errata. )

Page 134

There is an error on line 25 of 11-5.  The comp function is supposed to check that A, B, and op match the same fields in the transaction.  But there is a mistake in the line that checks this fact.  It should read as follows:

function bit comp (alu_operation t);
return ((t.A == A) && (t.B == B) && (t.op == op));

The line in the book is missing the second ‘=’ sign in the op comparison.  This is an error that makes VHDL-lovers chortle since this kind of error could not happen in VHDL.  In SystemVerilog (and Verilog and C) this kind of error causes t.op to take on the value of op.  It returns true as long as op is not zero.  While a linter would catch this problem, the SystemVerilog syntax checker will not.

Throughout the Book

If you look at section 6.19.5 of the SystemVerilog LRM, you’ll see that enumerated types have several methods that can be run on them.  If you look at section, you’ll see that enumerated types have a method called .name that returns a string that contains the value of the enumerated type in the variable.

The intention is that the following approach will return the name of the enumerated type in the variable op:

$sformat(str,"A: %2h  B:%2h   OP:%s", A,B,op.name);

However, throughout the book, I omitted the .name in these system calls and this worked in Questa. However, it does not work in Incisive. Incisive requires the .call to the name method..

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{ 7 comments… read them below or add one }

Robert L Tom April 7, 2010 at 11:33 am

I am applying all the errata to the book that I have in front of me and came across Page 350.

My book shows

bins bin_name ( <value1> => <value2> );

After applying the errata, it now shows

bins bin_name = ( <value1> = <value2> );

Should it be this

bins bin_name = ( <value1> => <value2> );

or this

bins bin_name = ( <value1> = <value2> );

Thanks. I can't wait to finish reading this book. It is a very good book.


ray April 7, 2010 at 12:37 pm

Wow. You're right. There's an errata on the errata. How recursive!

I've fixed it.


Liu,Li-Wu May 16, 2011 at 8:33 am

Hi Ray,
When I run the example of Reporting with IUS, this result is not same with yours.
The difference shows below:
1. **** action by severity
= DISPLAY (it doesn't show OVM_INFO)
^A= DISPLAY(it doesn't show OVM_WARRING)
^B= DISPLAY COUNT(it doesn't show OVM_ERROR)
^C= DISPLAY EXIT(it doesn't show OVM_FATAL)
2. *** ACTIONS by id and severity
always report this "NO ACTION" and can't be finished!!

Thanks for your response.


ray May 16, 2011 at 8:48 am

Hi Liu,

I'm not certain what you mean in your message. Do you mean the report looks different?
I wonder if OVM has changed since then.



Liu,Li-Wu May 19, 2011 at 7:00 am

Hi Ray,
I suffer a problem when running simulation about a reference to a tlm_fifo on the module port list. I list below:
module producer (ref tlm_fifo #(alu_operation) fifo);
The IUS10.2 doesn't support this feature, and Cadence FAE said this would be supported in a future release.
Could you inform me how to revise this to be workaround with IUS running?


ray May 19, 2011 at 8:12 am

Hi Liu,

You're the second person to mention this problem with IUS. There is probably a very ugly way to do this. Let me give it a little thought. I suspect that you can create a variable inside the module that holds the TLM fifo and then use Verilog hierarchical references to set the variable to the TLM fifo.

Also, be sure to tell your Cadence FAE that this has made a Mentor FAE very happy. That should motivate them to fix it faster 🙂



ray May 19, 2011 at 8:32 am

Hi Liu,

I have posted a solution to the IUS problem: http://www.fpgasimulation.com/?page_id=155


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