SystemVerilog Code Examples

This page contains links to coding examples.  All the files are .zip.  They can be unzipped in Windows with the built in decompression tool, and they can be unzipped in Linux with the “unzip” command:

• Example Code from FPGA Simulation—This file contains the source code examples from the book FPGA Simulation organized by chapter and section.
• SystemVerilog for VHDL Engineers—This file contains the PDF and the example files from the SystemVerilog Primer for VHDL engineers.
• macro_example.zip—This file shows you how to create macros in Verilog to make it easier to print messages to the screen with the OVM
• I2C Monitor—This example uses SystemVerilog and transaction-level design techniques to deliver a monitor for your I2C bus.  Attach the monitor to the bus and see the activity printed to the screen, or added to a Questa waveform.
• Code Coverage with Test Plan—This example shows how to create a simple test plan using Excel and import it into ModelSim.
• Transactions that work with Cadence’s IUS simulator—IUS doesn’t support putting object references into a Verilog port list. As a Mentor AE this kind of news fills me with evil glee. But from a broader perspective, it puts a crimp into the module-based transaction design style. I’ve found a solution to the problem and demonstrate it here. These examples replace the ones in Chapter 12.4 (which work with Mentor’s Questa simulator)

Download away!