SystemVerilog Code Examples

This page contains links to coding examples.  All the files are .zip.  They can be unzipped in Windows with the built in decompression tool, and they can be unzipped in Linux with the “unzip” command:

  • Example Code from FPGA Simulation—This file contains the source code examples from the book FPGA Simulation organized by chapter and section.
  • SystemVerilog for VHDL Engineers—This file contains the PDF and the example files from the SystemVerilog Primer for VHDL engineers.
  •—This file shows you how to create macros in Verilog to make it easier to print messages to the screen with the OVM
  • I2C Monitor—This example uses SystemVerilog and transaction-level design techniques to deliver a monitor for your I2C bus.  Attach the monitor to the bus and see the activity printed to the screen, or added to a Questa waveform.
  • Code Coverage with Test Plan—This example shows how to create a simple test plan using Excel and import it into ModelSim.
  • Transactions that work with Cadence’s IUS simulator—IUS doesn’t support putting object references into a Verilog port list. As a Mentor AE this kind of news fills me with evil glee. But from a broader perspective, it puts a crimp into the module-based transaction design style. I’ve found a solution to the problem and demonstrate it here. These examples replace the ones in Chapter 12.4 (which work with Mentor’s Questa simulator)

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New Example Design: I2C Monitor | FPGA Simulation
February 11, 2010 at 8:59 pm

{ 10 comments… read them below or add one }

Kubendra Kumbar October 27, 2009 at 6:06 pm

This is book is too good for understanding the basic concepts.


sachin August 2, 2012 at 1:02 am

Which book are you talking about?


ray August 2, 2012 at 7:51 am

I believe he's talking about FPGA SIMULATION (link to the right).


Liu,Li-Wu May 16, 2011 at 2:45 am

Is there any modification to run the do file in Cadence IUS simulator?


Sudipta Das July 15, 2011 at 3:10 pm

i2c code is not running… showing 2 error…can u give error free code of that one…


ray July 15, 2011 at 3:17 pm

Hi Sudipta,

When you say "showing 2 error" what do you mean?



Alon September 10, 2011 at 5:53 am

First of all, thank you for the amazing book.
I have a little question about something that i don't understand:
In chapter 25 , you talk about the "tester" module and you said that when you write this module you need to include the "test_constraint.svh" file.
I try to find this file in your examples to understand what this file contain, but I didn't find it.
I didn't find in this chapter description about this file neither.
Can you describe for me please what this file contain?



raysalemi September 11, 2011 at 5:22 pm

Hi Alon,

That file gets created by the script. The script copies the constraints out of the tests directory and then runs the test:

set contents [glob -directory tests *]
foreach item $contents {
file copy -force $item ./test_constraint.svh

You'll be able to see the test_constraint.svh file after you run the script.

Sorry for the confusion.



Nangavalli March 29, 2013 at 5:05 pm

Hi Ray,

Excellent book. I can understand verifying a module like "tiny ALU". In case, the module inside the Top FPGA, how to access the output of that module, can it be like .tinyalu(result)?


ray March 31, 2013 at 10:44 am

Hi Ram,

I answered your question on this page:



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