From the monthly archives:

February 2010

String Concatenation in SystemVerilog

by Ray Salemi on February 22, 2010

I just thought I’d share a cool feature of SystemVerilog: string concatenation. In Verilog, you can concatenate two numbers using the concatenation operator: {4′b1010,4′b1111} gives us 8′b10101111 Now SystemVerilog has extended the concatenation operator to strings so we can do this: `info(“TLM MEM”, {“Putting “,ak_ph.convert2string}) This gives us an output like this: # OVM_INFO @ [...]

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A Fun Book

by Ray Salemi on February 20, 2010

The next time you have a flight and want something to read, I recommend that you pick up a copy of Daemon. Suarez’s book is unapologetically technical and has a strong narrative drive that will make your flight pass quickly. The second book Freedom(TM) is a fitting conclusion and provides a thought provoking, and perhaps [...]

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A new high for FPGA Simulation

by Ray Salemi on February 14, 2010

Today FPGA Simulation: A Complete Step-by-step Guide achieved the highest rank I’ve ever seen on Amazon:  #44,381 overall and #16 in the Digital Design and the Modeling & Simulation categories.

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New Example Design: I2C Monitor

by Ray Salemi on February 11, 2010

I’ve added new example design to the SystemVerilog Code Examples page: an I2C monitor module.  This module has two ports: sda and scl.  You simply instantiate the module and attach sda and scl to get output such as this: If you are running Questa, the module is also able to put the transactions into the [...]

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