In order to put all the information and discussions in one place, I have moved the source code and book errata information from the FPGA Simulation forums to the central blog page. I’ve discontinued the forums since it’s easy to have discussions after blog postings.
The book FPGA Simulation uses code coverage as its basic measure and SystemVerilog to implement transaction-level simulation. This raises the question of whether there are any free SystemVerilog simulators that handle code coverage. The short answer is No. SystemVerilog is an enormous language, and while the original Verilog simulator was written by a single guy, [...]