From the monthly archives:

June 2009

Use SystemVerilog Macros for OVM Messaging

by Ray Salemi on June 29, 2009

Typing “ovm_top.ovm_report_…” can take a long time. Here’s a way to make it easy to use OVM messaging.

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A SystemVerilog Primer for VHDL Coders

by Ray Salemi on June 24, 2009

SystemVerilog is becoming the defacto standard for test bench creation, even in cases where the DUT is VHDL.  As more and more IP becomes available in SystemVerilog, even hard core VHDL engineers will need to have at least a passing aquaintance with the language. With that in mind, I’ve created a primer that teaches the […]


Using $psprintf in OVM Messages

by Ray Salemi on June 14, 2009

In FPGA Simulation, I showed you how to use the OVM reporting methods and how to include the module name in the messages for easier debugging.  The code looked like this, for example in Figure 13-1 in the book: module top; string m; initial begin $sformat(m,”%m”); ovm_top.set_report_verbosity_level(200); ovm_top.ovm_report_info (m,”Just Info”, 300, `__FILE__,`__LINE__); This example gives […]