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Verification IP

New Example Design: I2C Monitor

by Ray Salemi on February 11, 2010

I’ve added new example design to the SystemVerilog Code Examples page: an I2C monitor module.  This module has two ports: sda and scl.  You simply instantiate the module and attach sda and scl to get output such as this: If you are running Questa, the module is also able to put the transactions into the […]

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