From the category archives:

General Simulation

A Cautionary Tale

by Ray Salemi on September 18, 2011

Today I started preparation for an article I’m writing for fpgajournal.com on Focused Expression Coverage. I broke out the example code from FPGA Simulation and ran the example from chapter 2, section six. The simulation hung. This was puzzling, because it certainly ran when I wrote the book and nobody had mentioned the design hanging. […]

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Making your simulations go wicked fast

by Ray Salemi on April 12, 2010

This is a nice article about GateRocket.  GateRocket allows you to synthesize your FPGA and place it in an actual part.  Then it stimulates the FPGA using your test bench. Techfocus Media :: Best of Both Worlds.

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And now…Ray Salemi Live! (the crowd goes wild.)

by Ray Salemi on March 4, 2010

On April 14th I’ll be at the Mentor Graphics User Group meeting delivering a presentation called, “What Now?  Smoothly Adopting Verification Technologies.” The meeting is at the Westford Regency and there’s no charge.  It’s going to be fun, and I hope to see you there. You can sign up at this link: http://user2user.mentor.com/westford-ma-april-14-2010

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String Concatenation in SystemVerilog

by Ray Salemi on February 22, 2010

I just thought I’d share a cool feature of SystemVerilog: string concatenation. In Verilog, you can concatenate two numbers using the concatenation operator: {4’b1010,4’b1111} gives us 8’b10101111 Now SystemVerilog has extended the concatenation operator to strings so we can do this: `info(“TLM MEM”, {“Putting “,ak_ph.convert2string}) This gives us an output like this: # OVM_INFO @ […]

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A Useful Messaging Macro

by Ray Salemi on July 30, 2009

Here is an idea that I added to a recent test bench.  It is a verbose messaging macro: `define verbose(msg)ovm_top.ovm_report_info($psprintf(“%m”), msg,500); `define info(msg) ovm_top.ovm_report_info($psprintf(“%m”), msg); `define warning(msg) ovm_top.ovm_report_warning($psprintf(“%m”), msg,,`__FILE__,`__LINE__); `define error(msg) ovm_top.ovm_report_error($psprintf(“%m”), msg,,`__FILE__,`__LINE__); `define fatal(msg) ovm_top.ovm_report_fatal($psprintf(“%m”), msg,,`__FILE__,`__LINE__); This macro creates an OVM info message, but it gives it a verbosity of 500. This means that […]

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Virtual Box: Linux on your PC

by Ray Salemi on July 6, 2009

Sun’s free virtual machine, Virtual Box, let’s you run Linux on your PC or Mac. Here is some set up advice.

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Use SystemVerilog Macros for OVM Messaging

by Ray Salemi on June 29, 2009

Typing “ovm_top.ovm_report_…” can take a long time. Here’s a way to make it easy to use OVM messaging.

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A SystemVerilog Primer for VHDL Coders

by Ray Salemi on June 24, 2009

SystemVerilog is becoming the defacto standard for test bench creation, even in cases where the DUT is VHDL.  As more and more IP becomes available in SystemVerilog, even hard core VHDL engineers will need to have at least a passing aquaintance with the language. With that in mind, I’ve created a primer that teaches the […]

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Using $psprintf in OVM Messages

by Ray Salemi on June 14, 2009

In FPGA Simulation, I showed you how to use the OVM reporting methods and how to include the module name in the messages for easier debugging.  The code looked like this, for example in Figure 13-1 in the book: module top; string m; initial begin $sformat(m,”%m”); ovm_top.set_report_verbosity_level(200); ovm_top.ovm_report_info (m,”Just Info”, 300, `__FILE__,`__LINE__); This example gives […]

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VHDL Tutorial: Learn by Example

by Ray Salemi on May 4, 2009

Here is a very cool little site I found with examples of VHDL design.  A great learning tool. VHDL Tutorial: Learn by Example.

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