From the category archives:

4. Transaction-Level

More Lectures from FPGA Simulation online

by Ray Salemi on March 1, 2010

I am presenting a series of web lectures on the topics in the book FPGA Simulation.  You can view the lectures at www.verificationacademy.net, or just click on this link: Evolving FPGA Verification Capabilities Module | Verification Academy. This week we’ve added three lectures: Step 2: Test Planning Step 4: Transaction Level Test Benches Step 7: [...]

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New Example Design: I2C Monitor

by Ray Salemi on February 11, 2010

I’ve added new example design to the SystemVerilog Code Examples page: an I2C monitor module.  This module has two ports: sda and scl.  You simply instantiate the module and attach sda and scl to get output such as this: If you are running Questa, the module is also able to put the transactions into the [...]

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Free SystemVerilog Simulators?

by Ray Salemi on September 9, 2009

The book FPGA Simulation uses code coverage as its basic measure and SystemVerilog to implement transaction-level simulation.  This raises the question of whether there are any free SystemVerilog simulators that handle code coverage. The short answer is No.  SystemVerilog is an enormous language, and while the original Verilog simulator was written by a single guy, [...]

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Adding SystemVerilog Monitors to a VHDL Test Bench

by Ray Salemi on July 27, 2009

This posting introduces the idea of putting SystemVerilog modules into a VHDL design.

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