This is the time of year where we look back at how we did in the previous year (or decade) and resolve to do better. With that in mind, I recommend three possible new years resolutions regarding FPGA design and debug. You don’t need to add all three of these to your flow to see [...]
Today I wrote an article for FPGA Journal the explains Focused Expression Coverage (FEC). Enjoy!
I have an article on eeweb.com this week on State Machine Design. Enjoy!
I designed the transaction methodology in FPGA Simulation to make transaction level communication look like wire level communication. The idea was that you would put the TLM fifos on the port list, just as you do with wires, and you’d be able to use a familiar style in a new way. Sadly, the Cadence IUS [...]
I’ve just discovered an excellent way to keep up with news in the FPGA/EDA world. Amelia’s Fish Fry over at www.fpgajournal.com is a funny, irreverent, 10-minute, look at the week’s tech news. Listening to Amelia’s broadcast is much more rewarding than wading through emails and web pages.
I recently got a question about how to store a test plan in ModelSim and match it to code coverage data. I’ve uploaded the example to the SystemVerilog examples page. The example also shows you how to merge code coverage information from multiple tests. Enjoy, and feel free to post any questions about the example [...]
This morning FPGA Simulation was #6 in the Digital Design category on Amazon. It is the most popular FPGA Development book. It’s right after: GPS for Dummies Marine Diesel Engines Two-Stroke Engine Repair and Maintenance Digital Integrated Circuits I Got My Kindle! Now What Can I Do? A least for this morning, FPGA Designers dominate [...]
The next time you have a flight and want something to read, I recommend that you pick up a copy of Daemon. Suarez’s book is unapologetically technical and has a strong narrative drive that will make your flight pass quickly. The second book Freedom(TM) is a fitting conclusion and provides a thought provoking, and perhaps [...]
Today FPGA Simulation: A Complete Step-by-step Guide achieved the highest rank I’ve ever seen on Amazon: #44,381 overall and #16 in the Digital Design and the Modeling & Simulation categories.
I found an errata in FPGA Simulation today. It is in the syntax for defining coverage on transitions in a covergroup on page 350: bins bin_name = ( <value1> = <value2> ); The first “=” is missing on page 350.