Code Coverage Example with Test Plan

by Ray Salemi on June 30, 2010

I recently got a question about how to store a test plan in ModelSim and match it to code coverage data.  I’ve uploaded the example to the SystemVerilog examples page.  The example also shows you how to merge code coverage information from multiple tests.

Enjoy, and feel free to post any questions about the example here.

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We’re Number 6!

by Ray Salemi on April 26, 2010

number6

This morning FPGA Simulation was #6 in the Digital Design category on Amazon.  It is the most popular FPGA Development book.  It’s right after:

  1. GPS for Dummies
  2. Marine Diesel Engines
  3. Two-Stroke Engine Repair and Maintenance
  4. Digital Integrated Circuits
  5. I Got My Kindle!  Now What Can I Do?

A least for this morning, FPGA Designers dominate the list.

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Making your simulations go wicked fast

April 12, 2010

This is a nice article about GateRocket.  GateRocket allows you to synthesize your FPGA and place it in an actual part.  Then it stimulates the FPGA using your test bench.
Techfocus Media :: Best of Both Worlds.

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$onehot

March 5, 2010

If you are creating automatic stimulus using the randomize() method and you need a value to be one-hot, you can use the built in $onehot assertion.  This assertion returns a 1 if the value inside it is a one-hot.  The assertion looks like this:

assert(myreq.randomize() with{
[...]

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And now…Ray Salemi Live! (the crowd goes wild.)

March 4, 2010

On April 14th I’ll be at the Mentor Graphics User Group meeting delivering a presentation called, “What Now?  Smoothly Adopting Verification Technologies.”
The meeting is at the Westford Regency and there’s no charge.  It’s going to be fun, and I hope to see you there.
You can sign up at this link: http://user2user.mentor.com/westford-ma-april-14-2010

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More Lectures from FPGA Simulation online

March 1, 2010

I am presenting a series of web lectures on the topics in the book FPGA Simulation.  You can view the lectures at www.verificationacademy.net, or just click on this link:
Evolving FPGA Verification Capabilities Module | Verification Academy.
This week we’ve added three lectures:

Step 2: Test Planning
Step 4: Transaction Level Test Benches
Step 7: Functional Coverage with Covergroups

Enjoy

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String Concatenation in SystemVerilog

February 22, 2010

I just thought I’d share a cool feature of SystemVerilog: string concatenation.
In Verilog, you can concatenate two numbers using the concatenation operator:
{4′b1010,4′b1111} gives us 8′b10101111
Now SystemVerilog has extended the concatenation operator to strings so we can do this:
`info(“TLM MEM”, {“Putting “,ak_ph.convert2string})
This gives us an output like this:
# OVM_INFO @ 9279600: reporter [TLM MEM] [...]

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A Fun Book

February 20, 2010

The next time you have a flight and want something to read, I recommend that you pick up a copy of Daemon. Suarez’s book is unapologetically technical and has a strong narrative drive that will make your flight pass quickly. The second book Freedom(TM) is a fitting conclusion and provides a thought provoking, [...]

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A new high for FPGA Simulation

February 14, 2010

Today FPGA Simulation: A Complete Step-by-step Guide achieved the highest rank I’ve ever seen on Amazon:  #44,381 overall and #16 in the Digital Design and the Modeling & Simulation categories.

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New Example Design: I2C Monitor

February 11, 2010

I’ve added new example design to the SystemVerilog Code Examples page: an I2C monitor module.  This module has two ports: sda and scl.  You simply instantiate the module and attach sda and scl to get output such as this:
If you are running Questa, the module is also able to put the transactions into the waveform [...]

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