FPGA Simulation

This is the time of year where we look back at how we did in the previous year (or decade) and resolve to do better.  With that in mind, I recommend three possible new years resolutions regarding FPGA design and debug.  You don’t need to add all three of these to your flow to see results.  Any one of them will make a big difference:

• Start measuring code coverage before going to the lab—This simple step is the basis for faster lab debug.  Notice that I’m not saying improve the code coverage, I’m just saying measure it.  Get the number, publish the number, and then continue with your work.  You’ll see an improvement in your lab debug time by this simple step.
• Publish a simulation plan before you simulate—Create a list of features in your device under test, and create a list of ways that you’ll simulate them.  If nothing else, you can use the list of features in the lab to make sure you’ve tested all the necessary behavior.
• Add OVL assertions to your design—Assertions check to make sure that your blocks are following their protocols directly, and that the inputs to your design match your assumptions.  They catch bugs earlier in the simulation process, and this cuts debug time in half.

If you add any one of these steps to your design and simulation process, you’ll have a much less stressful 2010.

Happy New Year!

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