FPGA Debug, you can’t fix what you can’t see

by Ray Salemi on January 21, 2010

There’s nothing like referring to another blog posting that you agree with 100%.

The GateRocket technology mentioned here is very cool.  It synthesizes the design into your FPGA target and allows you to run your testbench on the actual hardware.

FPGA Debug, you can’t fix what you can’t see.

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New Year’s Resolution

by Ray Salemi on January 1, 2010

This is the time of year where we look back at how we did in the previous year (or decade) and resolve to do better.  With that in mind, I recommend three possible new years resolutions regarding FPGA design and debug.  You don’t need to add all three of these to your flow to see results.  Any one of them will make a big difference:

  • Start measuring code coverage before going to the lab—This simple step is the basis for faster lab debug.  Notice that I’m not saying improve the code coverage, I’m just saying measure it.  Get the number, publish the number, and then continue with your work.  You’ll see an improvement in your lab debug time by this simple step.
  • Publish a simulation plan before you simulate—Create a list of features in your device under test, and create a list of ways that you’ll simulate them.  If nothing else, you can use the list of features in the lab to make sure you’ve tested all the necessary behavior.
  • Add OVL assertions to your design—Assertions check to make sure that your blocks are following their protocols directly, and that the inputs to your design match your assumptions.  They catch bugs earlier in the simulation process, and this cuts debug time in half.

If you add any one of these steps to your design and simulation process, you’ll have a much less stressful 2010.

Happy New Year!

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Norway spiral video: Mystery solved

December 12, 2009

It seems to me that this Russian rocket test failure was the result of insufficient FPGA Simulation:

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Dang. Found an error.

December 4, 2009

I found an errata in FPGA Simulation today.  It is in the syntax for defining coverage on transitions in a covergroup on page 350:

bins bin_name = ( <value1> = <value2> );

The first “=” is missing on page 350.

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Verification Academy

December 3, 2009

I am now on the Verification Academy presenting Step 1 of the seven steps of verification : Code Coverage.
You can sign up for the Code Coverage presentation, and other topics in verification such as assertion based verification at the Verification Academy.
The URL is www.verificationacademy.net
Enjoy!

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OVM Reporting Severities

November 20, 2009

In chapter 13 of FPGA Simulation, I talk about controlling reporting through the ovm_top object, and on page 161 I talk about controlling actions based on OVM severities.  A call to ovm_top that mentions severities asks for a severity as an argument.  For example, here is a call that allows you to set the action [...]

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A little housekeeping

September 26, 2009

In order to put all the information and discussions in one place, I have moved the source code and book errata information from the FPGA Simulation forums to the central blog page. I’ve discontinued the forums since it’s easy to have discussions after blog postings.

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Free SystemVerilog Simulators?

September 9, 2009

The book FPGA Simulation uses code coverage as its basic measure and SystemVerilog to implement transaction-level simulation.  This raises the question of whether there are any free SystemVerilog simulators that handle code coverage.
The short answer is No.  SystemVerilog is an enormous language, and while the original Verilog simulator was written by a single guy, today’s [...]

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A Nice Presentation Resource

September 2, 2009

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A Useful Messaging Macro

July 30, 2009

Here is an idea that I added to a recent test bench.  It is a verbose messaging macro:

`define verbose(msg)ovm_top.ovm_report_info($psprintf(”%m”), msg,500);
`define info(msg) ovm_top.ovm_report_info($psprintf(”%m”), msg);
`define warning(msg) ovm_top.ovm_report_warning($psprintf(”%m”), msg,,`__FILE__,`__LINE__);
`define error(msg) ovm_top.ovm_report_error($psprintf(”%m”), msg,,`__FILE__,`__LINE__);
`define fatal(msg) ovm_top.ovm_report_fatal($psprintf(”%m”), msg,,`__FILE__,`__LINE__);

This macro creates an OVM info message, but it gives it a verbosity of 500. This means that the message will not show [...]

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