New Year’s Resolution

by Ray Salemi on January 1, 2013

This is the time of year where we look back at how we did in the previous year (or decade) and resolve to do better.  With that in mind, I recommend three possible new years resolutions regarding FPGA design and debug.  You don’t need to add all three of these to your flow to see results.  Any one of them will make a big difference:

  • Start measuring code coverage before going to the lab—This simple step is the basis for faster lab debug.  Notice that I’m not saying improve the code coverage, I’m just saying measure it.  Get the number, publish the number, and then continue with your work.  You’ll see an improvement in your lab debug time by this simple step.
  • Publish a simulation plan before you simulate—Create a list of features in your device under test, and create a list of ways that you’ll simulate them.  If nothing else, you can use the list of features in the lab to make sure you’ve tested all the necessary behavior.
  • Add OVL assertions to your design—Assertions check to make sure that your blocks are following their protocols directly, and that the inputs to your design match your assumptions.  They catch bugs earlier in the simulation process, and this cuts debug time in half.

If you add any one of these steps to your design and simulation process, you’ll have a much less stressful 2013.

Happy New Year!

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New article on Focused Expression Coverage

by Ray Salemi on September 28, 2011

Today I wrote an article for FPGA Journal the explains Focused Expression Coverage (FEC).  Enjoy!

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State Machine Design

September 22, 2011

I have an article on this week on State Machine Design. Enjoy!

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A Cautionary Tale

September 18, 2011

Today I started preparation for an article I’m writing for on Focused Expression Coverage. I broke out the example code from FPGA Simulation and ran the example from chapter 2, section six. The simulation hung. This was puzzling, because it certainly ran when I wrote the book and nobody had mentioned the design hanging. […]

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Fixing problem with Cadence’s IUS Simulator

May 19, 2011

I designed the transaction methodology in FPGA Simulation to make transaction level communication look like wire level communication. The idea was that you would put the TLM fifos on the port list, just as you do with wires, and you’d be able to use a familiar style in a new way. Sadly, the Cadence IUS […]

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Cool new FPGA News Source

December 1, 2010

I’ve just discovered an excellent way to keep up with news in the FPGA/EDA world.  Amelia’s Fish Fry over at is a funny, irreverent, 10-minute, look at the week’s tech news.  Listening to Amelia’s broadcast is much more rewarding than wading through emails and web pages.

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Code Coverage Example with Test Plan

June 30, 2010

I recently got a question about how to store a test plan in ModelSim and match it to code coverage data.  I’ve uploaded the example to the SystemVerilog examples page.  The example also shows you how to merge code coverage information from multiple tests. Enjoy, and feel free to post any questions about the example […]

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We’re Number 6!

April 26, 2010

This morning FPGA Simulation was #6 in the Digital Design category on Amazon.  It is the most popular FPGA Development book.  It’s right after: GPS for Dummies Marine Diesel Engines Two-Stroke Engine Repair and Maintenance Digital Integrated Circuits I Got My Kindle!  Now What Can I Do? A least for this morning, FPGA Designers dominate […]

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Making your simulations go wicked fast

April 12, 2010

This is a nice article about GateRocket.  GateRocket allows you to synthesize your FPGA and place it in an actual part.  Then it stimulates the FPGA using your test bench. Techfocus Media :: Best of Both Worlds.

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March 5, 2010

If you are creating automatic stimulus using the randomize() method and you need a value to be one-hot, you can use the built in $onehot assertion.  This assertion returns a 1 if the value inside it is a one-hot.  The assertion looks like this: assert(myreq.randomize() with{ $onehot(onehot_reg) == 1;}); This code will clear all the […]

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